//-*-mode:verilog-*-------------------------------------------------------
//
//  Copyright (c) 1999 Cornell University
//  Computer Systems Laboratory
//  Cornell University, Ithaca, NY 14853
//  All Rights Reserved
//
//  Permission to use, copy, modify, and distribute this software
//  and its documentation for any purpose and without fee is hereby
//  granted, provided that the above copyright notice appear in all
//  copies. Cornell University makes no representations
//  about the suitability of this software for any purpose. It is
//  provided "as is" without express or implied warranty. Export of this
//  software outside of the United States of America may require an
//  export license.
//
//  $Id: sysfunc.h,v 1.1.1.1 2003/01/16 19:49:43 heinrich Exp $
//
//-------------------------------------------------------------------------

//
//  Interface to system calls
//
task syscall;
   
   reg[31:0] i;
   
   begin
      // store register file state to the C interface functions!
      for (i=1; i<32;i=i+1)
	 begin
	    $builtin_setregvalue (i,CPU.regfile.RAM[i]);
	 end
      $builtin_setpc (CPU.PC);	// store PC

      // do the system call
      if ($builtin_syscall) begin
	 // exit called
	 $display ("-----------------------------------\n");
	 $display ("Program Terminated.\n");
	 $display ("Executed %d instructions\n", CPU.num_instructions);
	 $display_rate(CPU.num_instructions);
	 $display ("-----------------------------------\n");
	 $finish;
      end

      // restore register file state from the C interface
      for (i=1; i<32;i=i+1)
	 begin
	    CPU.regfile.RAM[i] = $builtin_regvalue(i);
	 end
   end
endtask

	 
			  

